Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important charge storage material for EEPROM devices is a charge storage layer in a charge trapping dielectric, for example, silicon nitride in an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes a charge trapping dielectric charge storage layer is a silicon-oxide-nitride-oxide-silicon (SONOS) type cell. In other such devices, the charge storage is in a charge trapping dielectric layer, but the materials of the various layers may vary from those used in SONOS devices. That is, the silicon, the oxide and/or the nitride of the respective layers may be replaced with another material. For example, silicon may be replaced by germanium or silicon-germanium, oxide and/or nitride may be replaced by, e.g., a high-K dielectric material. Such devices, as well as the SONOS device, are generally included within the designation “charge trapping dielectric flash memory” device, as used herein.
In charge trapping dielectric devices, during programming, electrical charge is transferred from the substrate to the charge storage layer in the charge trapping dielectric of the device, e.g., the nitride layer in a SONOS device. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom oxide layer and become trapped in the charge storage layer. This jump is known as hot carrier injection (HCI), the hot carriers being electrons. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the charge storage layer near the source region. Because the charge storage layer material is not electrically conductive, the charge introduced into the charge storage layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous charge storage layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a charge storage layer and have designed memory circuits that utilize two or more regions of stored charge within the charge storage layer. This type of non-volatile memory device is known as a dual-bit or multi-bit EEPROM. A dual-bit EEPROM is available under the trademark MIRRORBIT™ from Advanced Micro Devices, Inc., Sunnyvale, Calif. The MIRRORBIT™ dual-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left bit and a right bit are stored in physically different areas of the silicon nitride layer, in left and right regions of each memory cell, respectively. The above-described programming methods are used to enable the two bits to be programmed and read simultaneously. Each of the two bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions. The multi-bit memory cells recently have been developed, in which more than two bits can be stored in separate regions of a single charge storage layer of the flash EEPROM memory cell. As used herein, the term “dual-bit” refers to both dual-bit and higher-bit memory cells, unless otherwise specifically stated.
A key concept associated with the charge trapping dielectric flash memory device is that for the device to operate properly, both bits must be able to be written and read separately. If one of the bits is programmed, a reverse read on the programmed bit must sense a high Vt, i.e., a “0”, and a reverse read on the non-programmed bit must sense a low Vt, i.e., a “1”. Thus, a reverse read on the non-programmed bit, which is equivalent to a forward read on the programmed bit, must punch through the region of trapped charge in order to generate a high enough read current. If this does not happen, the non-programmed bit will not be able to be read as a “1”, i.e., a conductive bit.
One problem which has been encountered with charge trapping dielectric flash memory devices including a charge storage layer is the buildup of charge in the charge storage layer, and subsequent increases in Vt, as a result of exposure to ultraviolet radiation during fabrication, and particularly in Back End Of Line (BEOL) process steps, i.e., following formation of the flash memory cell. Processes which include high levels of UV radiation cause such charge buildup and concomitant increase in Vt. This increase in Vt would make all the bits appear to be high, i.e., “0”. In addition, if the charge buildup is sufficiently large, it cannot be easily erased by the available voltages. As a result, the charge trapping dielectric device would be rendered useless as a charge storage device.
UV exposure is not a problem for floating gate flash devices which have a polysilicon or other conductive material for a charge storage element. In such devices, the floating gate may be purposely exposed to UV radiation, in order to neutralize any electronic charge which builds up on the floating gate memory cell during processing. For example, U.S. Pat. No. 6,350,651 uses UV radiation in this manner.
Such processing is not an option for charge trapping dielectric flash memory devices, since the charge storage layer can be irreversibly damaged by exposure to UV radiation which builds up a large charge, and the charge cannot be neutralized by further exposure to UV radiation.
One proposed solution is to deposit over the interlevel dielectric (ILD) one or more layers that block a significant amount of UV radiation from reaching the charge storage layer, e.g., a UV blocking layer. The ability of the UV blocking layer to block harmful radiation is directly related to the variation in thickness of the UV blocking layer. Further, a smooth surface of the UV blocking layer is necessary to maintain photolithographic depth of focus for subsequent steps and also to ensure that contacts are formed over the source/drain regions. Conventional chemical mechanical polishing alone of the surface of the ILD layer results in significant variations in the thickness of the ILD surface, i.e., the surface topography, that significantly reduces the ability of the UV blocking layer to shield the charge storage layer and the ability to form with precision subsequent device features such as contacts. That is, the surface topography of the ILD layer is directly related to the device features it is formed over. For example, the surface topography increases significantly in height (thickness) over a SONOS device relative to the surface topography over a featureless semiconductor substrate. Although a conventional CMP process will reduce the variation in thickness of the ILD surface, depressions in the ILD will remain because the ILD layer is of the same material.
Therefore, a need exists for a method which will increase the planarization of the surface of the ILD, i.e., significantly reduce the thickness variations in the topography of the ILD. Further, there exists a need for a method which benefits from the increased planarization of the ILD and provides a device which includes protection of the charge storage layer in charge trapping dielectric devices from exposure to UV radiation during BEOL processing. Accordingly, advances in such fabrication technology are needed to insure that charge buildup and increase in Vt, in charge trapping dielectric structures does not occur, particularly during BEOL processing.